Line drivers are an important building block in a high-speed data transmission system. They are located at the very end of any transmitter system and encode the data symbols into a traveling wave signal to be transmitted over a line. A transmission line supports two wave propagation modes: forward transmission and reverse transmission. While the forward transmission wave contains the actual data symbol and represents the wanted signal, a reverse traveling wave may arise due to any impedance discontinuity between transmitter and receiver. Such an impedance discontinuity may result for example from the chip package and/or the connectors. The reverse traveling wave may then interfere with the wanted signal, which in turn degrades eye opening, jitter performance and bit error rate. To minimize such reflections, the transmission line must be terminated with its wave impedance, usually 50 Ohm, at the transmitter and at the receiver.
A simplified schematic of a typical conventional data transmission system is shown in FIG. 1. The line driver, illustrated in FIG. 1 on the left side of the data transmission system, consists of a pair of transistors M1, M1′ forming a differential input Vin+, Vin− that is biased with a current source (I1) and a resistive load R1 and R1′ respectively. The resistive load R1 and R1′ respectively acts as a transmission line termination. The receiver of the data transmission system is illustrated in FIG. 1 on the right side. As mentioned above, the line driver and the receiver are interconnected over the transmission line TL. The input of the receiver is terminated with resistors RT and RT′ respectively to a termination voltage supply VTT. To minimize reflections, the termination resistors R1, R1′ and RT, RT′ should be equal to the 50 Ohm wave impedance Rw of the transmission line TL.
One of the key figures of merit of a line driver is its output reflection coefficient S22, determined as the ratio between reflected wave and transmitted wave, and should be ideally zero.
                                          S            22                    ⁡                      (                          j              ⁢                                                          ⁢              ω                        )                          =                                            ɛ                              2                +                ɛ                                      -                          j              ⁢                                                          ⁢              ω              ⁢                                                          ⁢                              R                1                            ⁢                              C                1                            ⁢                                                1                  +                  ɛ                                                  2                  +                  ɛ                                                                          1            +                          j              ⁢                                                          ⁢              ω              ⁢                                                          ⁢                              R                1                            ⁢                              C                1                            ⁢                                                1                  +                  ɛ                                                  2                  +                  ɛ                                                                                                      wherein          ⁢                                          ⁢          ɛ                =                                            R              1                        -                          R              W                                            R            W                              
Any mismatch ε between termination impedance and wave impedance of the transmission line TL results in a finite reflection coefficient S22. The mismatch ε is mainly due to tolerances and variations in the chip fabrication process and/or the printed circuit board. 20% of impedance mismatch ε, for example, result in a 10% reflected wave at lower frequencies which can be several tens of MHz.
One solution to improve the low frequency impedance matching is described in “Digitally Adjustable Resistors in CMOS for High-Performance Applications”, T. J. Gabara, S. C. Knauer, IEEE Journal of Solid-State Circuits, vol. 27, no. 6, pp. 176–1185, August 1992. For this purpose, a tunable on-chip termination resistor that is controlled by an external reference resistor is implement in the line driver.
Two even more elaborate self-tuning schemes exist that do not need any external reference resistor and tune the on-chip termination resistor to the effective measured line impedance. They are described in “A Self-Terminating Low-Voltage Swing CMOS Output Driver”, T. Knight, A. Krymm, IEEE Journal of Solid-State Circuits, vol. 23, no. 2, pp. 457–464, April 1988 and “Automatic Impedance Control”, A. DeHon, T. Knight, T. Simon, Proc. IEEE Int. Solid-State Circuits Conference, vol. XXXVI, pp. 164–165, February 1993.
All the above mentioned schemes to improve impedance matching, however, are only effective at low frequencies. Even with perfect impedance matching where ε=0 the reflection coefficient S22 increases when the frequency increases, due to an unavoidable parasitic capacitance C1 and C1′ respectively at the driver's output. This parasitic capacitance C1, C1′ is dominated by electrostatic discharge (ESD) protection diodes that are required to guarantee a certain robustness against high voltages. ESD diodes must absorb or withstand a certain pulse energy or charge, therefore it is difficult to decrease their value of “parasitic” capacitance C1, C1′, not to mention that it may scale with technology. With increasing bit rate the impact of the capacitance C1, C1′ becomes more detrimental and has become a primary concern in I/O speeds>1 Gb/s.
To compensate the influence of the capacitance C1 at high frequencies a scheme exists that employs distributed ESD devices using on-chip transmission lines. Further explanations thereto can be found in “Distributed ESD Protection for High-Speed Integrated Circuits”, B. Kleveland, T. J. Maloney, I. Morgan, L. Madden, T. H. Lee, S. S. Wong, IEEE Electron Device Letters, vol. 21, no. 8, pp. 390–392, August 2000.
A second way to compensate the influence of the capacitance C1 at high frequencies is described in “Broadband ESD Protection Circuits in CMOS Technology”, S. Galal, B. Razavi, Proc. IEEE Int. Solid-State Circuits Conference, pp. 182–183, February 2003. For this purpose, on-chip coils are employed in the line driver.
Disadvantageously, both schemes considerably increase the area requirement per output, in particular the solution with distributed ESD protection. Furthermore, both solutions do not comply with any chip design methodology, where as much as 10 and more routing metal layers in several thicknesses and configuration options must be supported.